PCIe Characterization Engineer

About the role

We are looking for a hands‑on PCIe Characterization Engineer to perform post‑silicon electrical characterization and validation of high‑speed SerDes physical‑layer interfaces in a laboratory environment. The role involves conducting high‑speed measurements, analyzing signal integrity, and automating test workflows.

Key responsibilities

• Perform post‑silicon electrical characterization of PCIe, Ethernet, UFS, and LPDDR5 high‑speed interfaces.
• Conduct eye diagram, jitter, BER, and S‑parameter measurements using oscilloscopes, BERT, VNA and TDR equipment.
• Read and interpret schematics and PCB layouts, troubleshoot signal‑level issues at probe points.
• Develop and maintain Python scripts to automate laboratory measurements and documentation.
• Collaborate with cross‑functional engineering teams and document test procedures and results.

Required profile

• 5+ years of experience in post‑silicon characterization, HSIO validation, or memory electrical validation.
• Hands‑on experience with high‑speed SerDes PHYs, especially PCIe.
• Background working at a semiconductor, silicon, or systems company (SoC, GPU, networking, storage, automotive compute).
• Willingness to work on‑site in Palo Alto, CA.

Required skills

• PCIe and high‑speed SerDes interface knowledge.
• Eye diagram, jitter, BER, and S‑parameter measurement expertise.
• Proficiency with high‑speed oscilloscopes, bit error rate testers (BERT), vector network analyzers (VNA) and time‑domain reflectometry (TDR) equipment.
• Ability to read schematics and PCB layouts.
• Python scripting for test automation.