PCIe Characterization Engineer

About the role

We are looking for an experienced PCIe Characterization Engineer to lead post‑silicon electrical characterization and validation of high‑speed SerDes PHYs. The role is hands‑on, on‑site in Palo Alto, and involves testing, measurement, and debugging of PCIe, Ethernet, UFS, and LPDDR5 interfaces.

Key responsibilities

• Perform post‑silicon electrical characterization of high‑speed SerDes PHYs and memory interfaces, including eye diagram, jitter, BER, and S‑parameter measurements.
• Operate high‑speed oscilloscopes, bit error rate testers (BERT), vector network analyzers (VNA), and TDR equipment.
• Analyze schematics and PCB layouts to identify signal‑integrity issues and support hardware debugging.
• Develop and maintain Python scripts for test automation, data collection, and analysis.
• Document results and collaborate with cross‑functional engineering teams to improve interface performance.

Required profile

• 5+ years of experience in post‑silicon characterization, HSIO validation, or SerDes validation.
• Hands‑on experience with high‑speed electrical interfaces in a semiconductor or systems‑engineering environment.
• Ability to read and interpret schematics and PCB layouts for hardware‑level debugging.
• Willingness to work on‑site in Palo Alto, CA.

Required skills

• Python scripting for laboratory automation and data analysis.
• Proficiency with high‑speed oscilloscopes, BERT, VNA, and TDR equipment.
• Experience measuring and analyzing eye diagrams, jitter, BER, and S‑parameters.
• Signal‑integrity analysis and hardware debugging.