SoC Design Verification Lead

About the role

AheadComputing is hiring a SoC Design Verification Lead in Portland, Oregon. The role defines the overall SoC verification strategy, leads a DV team through emulation and FPGA prototyping workflows, and drives the team toward tape-out readiness.

Key responsibilities

• RISC-V TSO compliance verification, coordinated with the NOC environment, ensuring memory ordering across coherent agents
• CHI protocol verification, including coverage models and directed tests for CHI transactions, snoop filters and cache state transitions
• Drive the SoC to successful Linux boot in emulation, own the bring-up checklist and triage boot failures
• Coordinate firmware readiness, code coverage thresholds, patches and initialization sequences
• Verify debug, trace and run control, including JTAG, CoreSight and debug access ports
• Validate CSR read/write behavior across cores, APPLIC and interrupt routing and prioritization
• Build performance testbenches and regression infrastructure, correlate simulation results with architectural reference models and run architectural compliance tests
• Define the verification strategy, coverage closure and regression management, build and mentor the DV team, interface with IP vendors and own bug triage and resolution

Required profile

• Graduate degree (MS or PhD) in EE, CE, CS or a related field
• 10+ years of SoC/ASIC design verification experience, with at least 3 years in a lead or management role
• Deep expertise in UVM/SystemVerilog and experience with complex multi-core SoCs
• Strong understanding of SoC architecture, interconnects and memory subsystems
• Excellent communication skills and ability to work independently in a fast-paced startup environment

Preferred qualifications

• RISC-V verification, AMBA CHI or ACE protocol experience, and performance verification environments
• Experience with Siemens Veloce emulation and proFPGA prototyping
• Firmware co-verification and scripting with Python or Perl

What we offer

• Competitive compensation and benefits package
• Technical leadership opportunity and collaboration with engineers working on chiplet-based architectures
• Professional growth in an innovative startup environment
• A flexible and inclusive work culture in Portland, OR