Senior CPU Microarchitecture & Logic Design Engineer, Fetch and Decode

About the role

AheadComputing is looking for a Senior Staff CPU Design Engineer to design and implement high-performance CPU subsystems focused on optimal power, performance and area (PPA). The role works closely with cross-functional teams to refine microarchitecture and validate designs, and is based in Portland, Oregon or Austin, Texas.

Key responsibilities

• Define, develop and drive microarchitecture specifications for complex CPU subsystems, focusing on branch prediction, instruction fetch and instruction decode.
• Collaborate with the verification team to set up verification strategies for new designs.
• Support testbench development and help verify engineers test and debug core and subsystem-level RTL in simulation, prototyping platforms and silicon.
• Design and optimize front-end RTL to meet power, performance, area and timing goals.
• Coordinate with core-wide and cross-discipline teams to implement RTL in physical design, meeting layout, reliability, interface and testability requirements.
• Mentor junior engineers and contribute to long-term CPU core architecture roadmaps.
• Create and communicate technical details clearly to team members.

Required profile

• 5-10 years of experience in CPU microarchitecture and RTL design.
• Extensive experience with high-performance instruction fetch, branch prediction, instruction decode and instruction caches.
• In-depth knowledge of microprocessor frontend architecture, including PPA optimization trade-offs.
• Ability to anticipate physical design challenges and adapt quickly.
• Preferred: expertise in rapid instruction fetch, accurate branch prediction and high-bandwidth decoding, plus knowledge of prediction algorithms, prefetching and flush/clear recovery.
• Preferred: familiarity with RISC-V ISA and major extensions, and the ability to define work models, coding standards and design methodologies for large CPU projects.

Required skills

• Strong proficiency in SystemVerilog and hardware design methodologies.
• Expert use of Verilog simulators and emulators, waveform viewers, logic synthesis and place-and-route tools.

What we offer

• Competitive salary and benefits package.
• Professional growth opportunities in an innovative startup environment.
• Flexible and inclusive work culture in Portland, OR or Austin, TX.