Hardware Engineer, FPGA

About the role

Normal Computing is seeking an FPGA Design Engineer to bridge RTL and physical silicon. You will bring physics‑inspired ASIC designs to life on FPGA platforms for pre‑silicon validation and early software development, while also building test infrastructure for post‑silicon bring‑up.

Key responsibilities

• Lead selection, procurement, and bring‑up of FPGA prototyping platforms (e.g., HAPS, VCU118/VPK180, custom boards).
• Adapt and implement complex ASIC RTL onto FPGA targets, handling multi‑clock domains and timing closure.
• Integrate in‑house designs with third‑party IP and serve as the Xilinx/Vivado ecosystem expert.
• Design, implement, and validate high‑speed I/O, focusing on PCIe accelerator cards.
• Build FPGA‑based tester designs for silicon bring‑up, device characterization, and automated test environments.
• Develop software layers (Python/C++) for hardware abstraction, register‑map generation, and automated build/regression flows.
• Perform lab debugging of timing and functional issues using ILA, oscilloscopes, logic analyzers, and high‑speed link analysis.

Required profile

• Proven experience taking FPGA designs from RTL through timing closure to validated hardware, preferably in ASIC prototyping or high‑growth hardware environments.
• Expert‑level SystemVerilog and/or VHDL synthesis skills with deep proficiency in Xilinx Vivado.
• Hands‑on experience with PCIe, AXI/AHB, SPI, UART, JTAG and other common interfaces.
• Strong Python programming for automation, testing, and build tooling.
• Solid board‑level bring‑up and lab debugging abilities on real hardware.
• Startup mindset with the ability to work independently and collaboratively across teams.

Required skills

• SystemVerilog
• VHDL
• Xilinx Vivado (synthesis, place & route, timing closure, IP integration)
• PCIe interface design and debugging
• AXI/AHB, SPI, UART, JTAG protocols
• Python
• C++
• FPGA platforms (HAPS, VCU118, VPK180, custom boards)
• Hardware abstraction layer development
• Board bring‑up and lab debugging (ILA, oscilloscopes, logic analyzers, BER/eye‑diagram analysis)