Hardware Engineer, Physical Design

About the role

Normal Computing is seeking a seasoned Physical Design Engineer to lead the end‑to‑end silicon realization process. You will work closely with RTL, architecture, and DFT teams to translate complex ASIC architectures into tape‑out‑ready designs.

Key responsibilities

• Lead the full netlist‑to‑GDSII physical design flow, including floorplanning, power grid design, placement, clock‑tree synthesis, and place‑and‑route.
• Own static timing analysis, timing‑constraint creation, and timing sign‑off across all corners and modes.
• Optimize power, performance, area, power integrity (IR/EM) and crosstalk.
• Execute physical sign‑off checks (DRC, LVS, ERC, antenna) and ensure smooth handoff to the foundry.
• Collaborate on design and floorplan reviews to influence macro placement, pin assignments, and feasibility.
• Prepare tape‑out checklists, manage final stream‑out, and support post‑silicon debugging.

Required profile

• At least three successful tape‑outs from netlist to sign‑off, preferably on advanced nodes.
• Deep hands‑on experience with industry‑standard physical design tools.
• Strong problem‑solving instincts for backend debugging.
• Ability to thrive in fast‑paced, cross‑functional environments.

Required skills

• Innovus
• IC Compiler II
• Tempus
• PrimeTime
• Pegasus
• Calibre