Hardware Engineer – RTL Design

About the role

Normal Computing is building next‑generation AI‑enabled silicon. As an RTL Design Engineer you will create and verify the digital logic that powers its thermodynamic hardware, working closely with architecture, verification and physical design teams.

Key responsibilities

• Write synthesizable SystemVerilog RTL for datapaths, control logic, and memory interfaces.
• Develop microarchitecture specifications and translate high‑level concepts into implementable designs.
• Collaborate with verification engineers to define test plans, debug issues, and achieve high coverage using both simulation and formal methods.
• Partner with physical design to meet timing, area, and floor‑planning constraints.
• Participate in design reviews, contribute to architectural decisions, and support tape‑out preparation.
• Assist with post‑silicon bring‑up as needed.

Required profile

• Hands‑on experience writing production RTL in SystemVerilog and closing designs through synthesis and place‑and‑route.
• Successful delivery of at least one tape‑out on any technology node.
• Proven ability to work on datapaths, pipelines, or custom logic where microarchitecture evolves during development.
• Strong debugging skills across simulation waveforms and formal counter‑examples.
• Experience collaborating directly with architects and physical designers without heavy intermediaries.
• Background in ASIC or SoC design.

Required skills

• SystemVerilog
• RTL design
• Synthesis and place‑and‑route
• Digital verification (simulation & formal)
• Microarchitecture development
• Physical design collaboration
• ASIC/SoC design flow
• Design‑for‑test (DFT) concepts

What we offer

• Opportunity to shape novel computing architectures from first principles.
• Work with a multidisciplinary team across New York, Silicon Valley, London, Copenhagen, and Seoul.
• Competitive compensation and equity in a fast‑growing AI hardware startup.