Front-End Power Engineer

About the role

Etched builds AI chips tailored to specific model architectures, aiming for higher throughput and lower latency than general-purpose GPUs. It is hiring a Front-End Power Engineer in Cupertino, working with the physical design team to meet power targets through the synthesis, place-and-route and sign-off phases.

Key responsibilities

• Optimize RTL designs to improve power efficiency while meeting performance and area goals.
• Apply power-saving techniques in RTL, such as clock gating, power gating, multi-voltage domains and dynamic voltage scaling.
• Estimate power and evaluate PPA trade-offs for new and existing design features.
• Work with the physical design team to ensure power targets are met during synthesis, place-and-route and sign-off.
• Create power models from RTL simulations and gate-level netlists, and perform power roll-up analysis to estimate chip-level power under different conditions.

Required profile

• RTL development experience with Verilog/SystemVerilog, focused on low-power design and optimization for complex digital systems.
• Knowledge of low-power techniques such as clock gating, power gating and DVFS.
• Familiarity with synthesis and place-and-route processes optimized for power.

Required skills

• Verilog/SystemVerilog
• Clock gating, power gating, DVFS
• Synthesis and place-and-route
• Nice to have: UPF/CPF power intent specifications
• Nice to have: power analysis tools such as Synopsys PrimePower or Cadence Joules
• Nice to have: automation of power analysis with Tcl, Perl or Python

What we offer

• Full medical, dental and vision coverage, with 100% of premiums paid by the employer
• Housing subsidy of $2,000 per month for those living within walking distance of the office
• Daily lunch and dinner provided in the office
• Relocation support for people moving to Cupertino