Power Optimization Engineer

About the role

Etched builds AI chips hard-coded for individual model architectures, aiming for higher throughput and lower latency than current GPU-based solutions. It is hiring a Power Optimization Engineer in its fully in-person Cupertino team, working with architects, performance engineers, software engineers, ASIC design engineers and physical design teams to deliver designs optimized for power.

Key responsibilities

• Develop the chip power model from the chip architecture and estimate chip power from the microarchitecture.
• Devise power-saving techniques tailored to product use cases.
• Implement design-for-optimal-power using advanced power management techniques.
• Estimate and analyze power consumption at full-chip and unit levels, guide ASIC teams to improve power efficiency before and after silicon, and correlate estimates with measurements.

Required profile

• Experience optimizing power with dynamic voltage and frequency scaling, power-aware synthesis, glitch power reduction and efficient power delivery networks.
• Experience with gate-level power optimization using VCD-based and/or FSDB-based power analysis.
• Strong understanding of energy consumption, estimation, data movement, low-power design and power-saving features.

Required skills

• Preferred: digital design and optimization with industry-standard power analysis tools and methodologies.
• Preferred: RTL and layout-level power optimization with PrimePower, VCD-based analysis, DVFS, clock power reduction, clock gating and glitch reduction.

What we offer

• Full medical, dental and vision coverage, with 100% of premiums covered.
• Housing subsidy of $2,000 per month for those living within walking distance of the office.
• Daily lunch and dinner provided in the office.
• Relocation support for people moving to Cupertino.