ASIC Timing Engineer

About the role

Etched builds AI chips tailored to specific model architectures, and is looking for an ASIC Timing Engineer to drive timing analysis and closure of its next-generation AI chips. The role works at block, cluster and full-chip level and collaborates with Physical Design, DFX, Clocks and other teams.

Key responsibilities

• Drive timing analysis and closure of chips at block, cluster and full-chip level
• Develop timing closure strategies, create timing constraints and ensure timing and power convergence, as well as ECO implementation
• Improve timing convergence flows together with the methodology teams
• Help understand DFT logic and assist with DFT timing closure for modes such as scan and BIST
• Work on timing closure of digital logic and macros in AMS designs and IPs

Required profile

• BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years of experience, or MS (or equivalent) with 2+ years in Timing and STA
• Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing convergence, timing constraint generation and management
• Ability to analyze and fix timing paths through ECOs, with a focus on crosstalk and noise analysis
• Familiarity with deep sub-micron process nodes, including modeling and convergence
• Background in domain-specific STA, especially GPUs, CPUs, DPUs/network processors or SoCs
• Experience in methodology and/or flow development, and automation

Required skills

• STA tools such as Fishtail and Lint
• CDC and RDC checks
• RTL to netlist knowledge and industry-standard STA and timing convergence tools

What we offer

• Full medical, dental and vision coverage, 100% of premiums paid, 90% for dependents
• Housing subsidy of $2,000 per month for those living within walking distance of the office
• Daily lunch and dinner in the office
• Relocation support for people moving to Cupertino