FPGA Verification Engineer – Air Dominance & Strike

About the role

We are seeking an FPGA Verification Engineer to join our fast‑growing team in Costa Mesa, CA. You will own verification of FPGA/SoC designs on AMD (Xilinx) platforms for flight‑critical avionics, applying UVM‑based, coverage‑driven methodologies.

Key responsibilities

• Architect and implement UVM verification environments (drivers, monitors, predictors, scoreboards) for AMD Xilinx FPGA/SoC designs.
• Develop verification plans, functional coverage models, and SystemVerilog Assertions (SVA) linked to system and hardware requirements.
• Create constrained‑random and transaction‑level test sequences, maintain regression suites, and track coverage metrics.
• Debug failures using waveform tools, collaborate on RTL reviews, and support hardware validation and board bring‑up.
• Ensure verification complies with DO‑254 and other safety standards, and produce closure reports.

Required profile

• Bachelor’s degree in Electrical or Computer Engineering (or related field).
• 2+ years of FPGA/ASIC verification experience with SystemVerilog and UVM.
• Eligibility to obtain a U.S. Secret security clearance.

Required skills

• SystemVerilog, UVM methodology, SystemVerilog Assertions (SVA).
• Industry simulators such as Questa, VCS, Xcelium, Vivado.
• Git, Linux development environments, Python, Tcl, Makefile.
• Digital interfaces: Ethernet, PCIe, JESD204C, MIL‑STD‑1553, SPI.
• Experience with AMD/Xilinx FPGA platforms and ARM‑based SoC.