FPGA Verification Engineer – Air Dominance & Strike

About the role

We are seeking an FPGA Verification Engineer to develop and execute verification environments for AMD (Xilinx) FPGA/SoC designs supporting air dominance and strike systems. The role involves creating UVM testbenches, authoring assertions, and ensuring compliance with DO‑254 safety standards.

Key responsibilities

• Architect and implement UVM verification environments, including drivers, monitors, predictors, and scoreboards.
• Develop verification plans, functional coverage models, and constrained‑random test sequences to achieve coverage closure.
• Debug failures using waveform tools, collaborate on RTL reviews, and support hardware bring‑up on target platforms.
• Maintain regression suites, track coverage metrics, and produce verification closure reports.

Required profile

• Bachelor’s degree in Electrical or Computer Engineering (or related field).
• 2+ years of experience in FPGA/ASIC verification with SystemVerilog, UVM methodology, and SVA.
• Proficiency with industry simulators (Questa, VCS, Xcelium, Vivado) and Git‑based collaborative workflows.
• Eligibility to obtain a U.S. Secret security clearance.

Required skills

• SystemVerilog, UVM, SVA
• Python, Tcl, Makefile scripting
• Git, Linux development environment
• Simulation tools: Questa, VCS, Xcelium, Vivado
• Digital interfaces: Ethernet, PCIe, JESD204C, MIL‑STD‑1553, SPI
• CI/CD integration and Nix‑based build environments