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Senior Firmware Engineer, Edge AI / NPU Runtime

tacit · San Francisco

Senior 🇬🇧 English
Embedded inference runtimes Vendor NPU/DSP SDKs DMA Ring buffers Deterministic scheduling Low-power firmware techniques

Job description

About the role

We are seeking a Senior Firmware Engineer to lead the Edge AI and NPU runtime stack for our next‑generation neurotech hardware. In this hands‑on position you will design, optimize, and ship production‑grade firmware that powers real‑time sensor acquisition, on‑device inference, and telemetry.

Key responsibilities

  • Deploy machine‑learning models onto embedded targets using NPUs, DSPs, MCUs, or other accelerators.
  • Integrate vendor NPU/DSP SDKs and embedded inference runtimes into production firmware.
  • Optimize inference latency, memory footprint, throughput, and power consumption.
  • Build end‑to‑end sensor‑to‑inference pipelines with DMA, interrupts, ring buffers, and deterministic scheduling.
  • Support streaming inference patterns such as sliding windows and event‑driven execution.
  • Implement low‑power techniques (sleep states, duty cycling, clock scaling) to minimize energy per inference.
  • Debug and bring up firmware across sensors, accelerators, power systems, and embedded compute using lab tools, traces, logs, and telemetry.

Required profile

  • Senior‑level experience in embedded firmware development.
  • Hands‑on expertise working close to hardware and low‑level system components.
  • Proven ability to meet tight latency, reliability, and power budgets in real‑world conditions.

Required skills

  • Embedded inference runtimes and vendor NPU/DSP SDKs.
  • Real‑time sensor acquisition, preprocessing, and feature extraction.
  • DMA, interrupt handling, ring buffers, deterministic scheduling.
  • Low‑power firmware techniques (sleep states, duty cycling, clock scaling).
  • Profiling and power‑consumption analysis across sensors, CPU, NPU/DSP, and memory.

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Source : ats:ashby

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Published 3 weeks ago

Expires 1 month from now

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tacit

San Francisco