Static Timing Analysis Manager (STA) - AI, Edge and Automotive Processors

About the role

NXP's AI and Chip Engineering SoC Implementation team is looking for a Static Timing Analysis (STA) Manager in Austin. You will lead a team of engineers working on AI, Edge and Automotive processors, on fast-paced, advanced-node SoC technologies. The role is central to the SoC implementation organization's charter to build world-class MPUs.

Key responsibilities

• Manage timing analysis activities for MPU SoCs, including constraint generation, verification and full-chip timing closure across all modes and scenarios
• Develop, implement and verify STA constraints, and close subsystem and SoC-level timing efficiently
• Apply knowledge of timing closure, physical design, floorplanning and place-and-route industry standards
• Collaborate with architecture and RTL teams to influence early design decisions and work with RTL, DV, DFT, EDA vendors and DTCO teams
• Contribute to timing flow and methodology improvements and coordinate with methodology teams
• Work with global design teams on large SoC projects and adapt quickly to the use of AI and agents in STA and physical design

Required profile

• BS or MS in Electrical or Computer Engineering
• 15+ years of experience in physical design for complex SoCs
• At least 3 years in STA lead roles
• Strong oral and written communication skills
• Experience working with multi-site teams is a must

Required skills

• Full-chip timing analysis, including crosstalk, noise, OCV and timing margins
• Familiarity with clock specs, jitter, IR drop and SPICE analysis
• Basic Verilog to collaborate with RTL and IP teams on timing fixes