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Principal Verification Engineer

nxp · Austin (Oakhill

New
Senior 🇬🇧 English
SystemVerilog Verilog VHDL UVM OVM Formal verification SVA DDR PCIe AMBA Python Perl UNIX/Linux

Job description

About the role

NXP is hiring a Principal Verification Engineer in Austin for its MME MCU/MPU Digital IP team. The team develops digital IPs for NXP's automotive and advanced microcontroller businesses, delivering sensor and processing technologies for connected and autonomous vehicles. The role drives a zero-defect mindset, provides technical leadership on complex verification challenges and mentors a small team of engineers.

Key responsibilities

  • Define and execute verification plans
  • Develop and implement verification testbenches, including drivers, monitors, scoreboards and advanced UVM VIPs
  • Develop directed and constrained-random stimulus
  • Analyze RTL, functional coverage and assertion coverage results, and define functional coverage models
  • Develop and maintain SystemVerilog assertions (SVA)
  • Apply formal verification methodologies
  • Debug failures, reproduce them and perform root-cause analysis
  • Mentor and grow a small team of engineers

Required profile

  • BSEE with 5+ years of semiconductor industry experience, or
  • MSEE with 3+ years of experience, or
  • PhD with 1+ year of experience
  • Strong debugging, analytical and problem-solving skills

Required skills

  • Knowledge of protocols such as DDR, PCIe and AMBA (CHI, ACE, AXI)
  • Strong expertise in Verilog and SystemVerilog (VHDL is a plus)
  • OVM/UVM and class-based verification, and formal verification
  • Experience using AI/LLM approaches to improve engineering efficiency
  • Test pattern debugging on simulation and automated test environments
  • Scripting in Python, Perl and UNIX/Linux
  • Familiarity with functional and code coverage methodologies

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Source : ats:workday

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Published 6 hours ago

Expires 1 month from now

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nxp

Austin (Oakhill