Principal Physical Design Engineer - SoC

About the role

NXP is looking for an experienced Principal Physical Design Engineer for SoC implementation in Austin, Texas. The role owns end-to-end physical design execution across complex designs, driving delivery from RTL to silicon for advanced technology nodes, with the aim of delivering optimized PPA (power, performance, area) and cost efficiency.

Key responsibilities

• Lead physical design execution including floorplanning, synthesis, place and route, CTS, routing, STA, PDN, PDV and signoff, and drive timing, power, IR/EM and physical verification closure to tapeout readiness.
• Mentor team members, model execution discipline and review mechanisms, and report status to senior leadership.
• Define and deploy next-generation physical design methodologies, drive automation and flow optimization, and lead adoption of advanced node technologies (5nm and beyond).
• Work with architecture, RTL, verification and product teams, and interface with EDA vendors and IP providers; support post-silicon bring-up, yield improvement and production ramp.

Required profile

• Bachelor's or Master's degree in Electrical or Electronics Engineering or a related field.
• 10+ years of experience in ASIC / SoC physical design.
• Preferred: experience in high-reliability SoCs and exposure to AI-driven design methodologies and automation.

Required skills

• RTL-to-GDSII implementation flow (Cadence and/or Synopsys tool sets)
• Floorplanning, synthesis, PNR, CTS, routing, STA and signoff
• Physical verification (DRC/LVS/ERC)
• Advanced node implementation (<=16nm / 5nm) and low-power design (UPF/CLP)
• Scripting in Python, TCL and Perl