Principal DFT Engineer

About the role

NXP is hiring a Principal DFT Engineer in Austin (Oakhill) to join a team working on leading-edge projects in the MCU & MPU Engineering & Design Enablement (MMEDE) business unit. MMEDE provides the technology and ecosystem relationships for next-generation automotive processing, edge processing and radar processing products.

Key responsibilities

• Handle RTL design for DFT-related changes at subsystem and top level, insert MBIST RTL for memories and verify it
• Analyze Scan DRCs and fix them in RTL
• Analyze ATPG coverage reports, devise mechanisms to improve coverage and generate patterns for ATE
• Insert TAP, IOs and test pinmux using NXP DFT flows
• Run power-aware RTL/GLS simulation bringup and maintain the regression suite for non-ATPG and ATPG simulations
• Bring up patterns on wafer probe and final test, working closely with Product and Test teams

Required profile

• DFT engineer with 5+ years of experience implementing and verifying scan architectures, JTAG, memory BIST and ATPG
• Self-driven, results-oriented, empathic communicator and team player willing to take on new challenges
• Well versed in digital design concepts, preferably with Verilog/VHDL RTL coding knowledge

Required skills

• Preferred: scan insertion, JTAG, ATPG DRC and coverage analysis
• Preferred: simulation debug with timing/SDF and root cause analysis of simulation failures