Hardware Security Architect (SoC)

About the role

NXP is looking for a SoC Security Architect in Austin (Oakhill) who defines and drives the hardware security architecture for SoCs across a range of end applications. The role owns and establishes the vision for future generations of security hardware, with deep expertise in hardware security and HW/SW interaction.

Key responsibilities

• Define SoC hardware security architecture and requirements, including HSM specification, secure boot/RoT concepts and cryptographic IP integration strategies (AES/SHA/PKA/PUF/PQC etc).
• Translate security features into high-level HW/SW specifications and derive HW requirements for product design.
• Lead threat modeling, risk assessments and vulnerability analysis, turning them into architectural mitigations and design constraints.
• Architect HW/SW security boundaries and co-design flows for secure boot, firmware services, drivers and runtime protection.
• Define secure key storage/provisioning (eFUSE/OTP) and security-aware DFT/TEST strategies balancing coverage and attack resistance.
• Collaborate with architecture, RTL, verification, DFT, PD and software teams to embed security into implementation and validation flows.
• Ensure compliance with cybersecurity standards such as ISO 21434, optimize for PPA trade-offs and drive system-level security validation.
• Stay current on threats and standards, and lead reviews and security guidance.
• Support customer discussions, audits and security reviews, and ensure security, safety and system-level design compliance (e.g. ISO 26262, IEC 61508).

Required profile

• Bachelor's or Master's degree in Electrical/Electronic/Computer Engineering or a related field.
• 10-15+ years of experience in SoC or MCU design with a strong focus on hardware security architecture and HW/SW interaction.
• Proven experience with threat modeling, risk assessment, security validation and vulnerability analysis for SoC-based systems.
• Excellent written and verbal communication skills for specifications, reviews and stakeholder alignment.

Required skills

• Strong understanding of SoC architecture, AMBA/AXI-class interconnects, memory subsystems and how security policies are enforced across HW/SW boundaries.
• Hands-on background with RTL design, synthesis concepts and EDA flows sufficient to review and guide secure implementation.