FPGA Engineer - Host and Network IO

About the role

Cerebras Systems builds a large AI chip and its Host and Network IO team develops the full IO path from server nodes through the cluster to the custom RoCE network stack and the proprietary IOs onto the WSE. As an FPGA developer on the team, you will own the in-chassis IO subsystem: several cluster-facing RoCE v2 network interfaces using a custom RDMA implementation, a large programmable switching fabric, and serial IO to the WSE via a proprietary protocol. You will work with AI application, cluster architecture and embedded software teams to optimise bandwidth and latency while minimising congestion and pauses.

Key responsibilities

• Lead full chassis-to-wafer IO architecture and design
• Improve current RTL, implement next-generation FPGA designs and define future IO architectures
• Produce production-ready bitstreams for deployment into large clusters running customer inference services
• Work with the DV team to prevent bug slips and simplify debugging
• Optimise bandwidth and latency over the FPGA datapath and all IO interfaces
• Interface with the board team to facilitate and execute board bring-up
• Drive network performance debugging of large AI clusters
• Integrate leading-edge networking technologies and protocols
• Lead cross-functional technical projects and foster clear communication across teams and stakeholders

Required profile

• 5+ years of industry experience delivering production FPGA solutions, or a Master's/PhD in Computer or Electrical Engineering plus 3 years of industry experience
• Highly productive with FPGA placement and routing, timing closure, simulation, debug and other FPGA workflows
• Knowledge of network switch environments or willingness to learn (e.g. Arista, Juniper)

Required skills

• Verilog development in a Git-based repository
• Familiarity with network protocols (TCP, RoCE) and network debug tools such as Wireshark