AI/ML Driven ASIC Design and Implementation Automation Engineer

About the role

NXP is hiring an AI/ML driven ASIC Design and Implementation Automation Engineer in its Advanced Chip Engineering (ACE) organization, based in San Diego. The role explores methodologies, flows and tools to improve power, performance, area and quality for SoC and IP development teams, and works with AI/ML and automation experts in industry and academia to define the methods and tool features needed for ASIC design.

Key responsibilities

• Develop prototype solutions evaluating state-of-the-art AI/ML techniques to find the best fit for NXP designs, while working on actual designs and implementations to pilot and develop the automation.
• Explore research ideas and solutions that bring AI/ML applications to VLSI design.
• Work with academic research communities in AI/ML for VLSI design, architecture teams, IP and SoC designers, and SoC implementation teams across multiple sites.
• Apply GenAI, reinforcement learning, graph neural networks and convolutional networks to automation applications.
• Drive cross-functional initiatives with Architecture, IP and SoC design, verification and implementation teams to support digital transformation.

Required profile

• BS or MS in Computer Science, Electrical Engineering, Computer Engineering or a related discipline, with a strong background in software development.
• 5+ years of hands-on experience in AI and ML techniques (LLMs, CNN, RNN, GraphNN) applied to real-world optimization problems.
• Knowledge of data structures, algorithms and software development for optimization problems.
• Hands-on experience with Unix/Linux, Git and BitBucket, software development and debug tools.
• Strong analytical problem-solving and verbal/written communication skills.

Required skills

• Python/C++
• Unix/Linux, Git, BitBucket
• Desirable: design, layout and constraint concepts (SDC, clocks, CDC, RDC), static timing analysis, low-power and power-aware flows (UPF)
• Desirable: VLSI CAD methodology and tool development, HDL (System Verilog, Verilog, VHDL), EDA tools for design, verification, DFT and implementation, and CI/CD tools (Jenkins, LSF, Make, Splunk)

What we offer

• Base salary range of $125,000 to $171,900 per year, with competitive benefits, incentive compensation and/or equity for certain roles.
• Health, dental and vision insurance, 401(k) and paid leave.