Senior ASIC RTL Design Engineer, AI Hardware

About the role

Cerebras Systems builds the world's largest AI chip, the Wafer Scale Engine (WSE), which delivers training and inference speeds over 10 times faster than GPU-based cloud services. As a senior front-end design engineer, you will join the team designing the next generation of WSE chips, working closely with design verification, physical design, software and system teams to bring semiconductor architectures from concept to production.

Key responsibilities

• Drive all aspects of chip design, including functional specification, micro-architecture, RTL development and synthesis.
• Work with the physical design team to close design and meet PPA goals.
• Work with design verification and DFT teams to achieve the best functional and test coverage.
• Collaborate with software and system teams to deliver optimal performance and feature set.
• Debug silicon-level functional, timing and power issues during bring-up.

Required profile

• Master's degree in Computer Science, Electrical Engineering or equivalent.
• 8+ years of experience delivering complex, high-performance RTL designs.
• Proven track record of multiple silicon successes.
• Experience with front-end chip integration and third-party IP integration.
• Experience in high-performance computing, GPU/CPU designs, machine learning or related fields.
• Ability to work in a hybrid environment; location is Sunnyvale, CA (open to remote).

Required skills

• RTL design and integration.
• Networking stack: TCP/IP, RDMA and Ethernet.
• Knowledge of PCIe, CPU interfaces and SerDes.
• Scripting tools: Python, TCL.
• Plus: FPGA place-and-route, floor planning and timing analysis; managing external ASIC vendors.

The base salary range is $200,000 to $290,000 per year, with possible bonus and equity.