Research Engineer, Chip Design RL (Reinforcement Learning)

About the role

Anthropic is looking for a Research Engineer to join its Code RL team and advance the ability of large language models to design silicon. You will translate chip‑design expertise into reinforcement‑learning tasks and signals, helping Claude excel at hardware design challenges.

Key responsibilities

• Invent, design, and implement RL environments and evaluation pipelines for agentic RTL generation, formal verification, and physical‑design optimization.
• Optimize cross‑cutting RL aspects such as EDA‑tool latency and proxy reward design.
• Run experiments, analyze results, and shape the research roadmap.
• Deliver research prototypes into production training runs.
• Collaborate with researchers, engineers, and safety teams across Anthropic.

Required profile

• Deep expertise in ASIC or FPGA design, including RTL, verification, and physical design.
• Hands‑on experience with tape‑out chips, taking designs from specification to silicon.
• Proficiency with industry EDA tools and processes.
• Ability to balance exploratory research with engineering implementation.
• Strong interest in AI safety and the development of beneficial systems.

Required skills

• ASIC design
• FPGA design
• RTL
• UVM
• Formal methods
• Coverage‑driven verification
• Physical design (synthesis, place‑and‑route, timing closure)
• PPA optimization
• DFT
• ECOs
• EDA tools
• Reinforcement learning