Principal Network Systems Architect

About the role

Cerebras Systems builds the world's largest AI chip, designed for ultra-fast training and inference. As Principal Network Systems Architect, you will define the scale-out and especially scale-up network architecture for current and future Cerebras platforms, including proprietary accelerator interconnects, protocols and switching. You will work with application, compiler, runtime and systems teams to turn communication patterns, workload placement, data and memory movement, synchronization and failure behavior into measurable fabric requirements.

Key responsibilities

• Set the multi-generation architecture and roadmap for Cerebras scale-up networks and their interfaces to scale-out and customer-facing networks.
• Work with application, compiler, runtime and communication-library teams to derive the required bandwidth, latency, ordering, availability and serviceability.
• Define fabric topology, protocols and switch behavior, including routing, buffering, flow control, reliability and fault containment.
• Decide when to use standards-based technology or merchant silicon versus custom protocols, switches, links or offloads.
• Use performance models, traffic simulation, prototypes and lab data to test architecture choices and set acceptance criteria.
• Write architecture and interface specifications, lead design reviews and drive cross-layer decisions through implementation, bring-up and qualification.

Required profile

• BS, MS or PhD in Electrical Engineering, Computer Engineering, Computer Science or a related field, or equivalent practical experience.
• Typically 12+ years of relevant industry experience, including principal-level ownership of a major networking, switching, accelerator or HPC system from architecture to implementation or deployment.
• Deep expertise in low-latency or proprietary interconnects, fabric protocols, switch architecture or a closely related area.
• Experience deriving network requirements from incomplete workload and system information, and a record of influencing engineering leaders, suppliers and customers.

Required skills

• Working knowledge of Ethernet, IP and RDMA, and conceptual familiarity with BGP and EVPN.
• Preferred: proprietary interconnects such as NVLink, xGMI, TPU ICI, PCIe, CXL, RoCE or InfiniBand; switch ASIC, NIC or DPU work; FPGA architecture; AI/HPC stacks such as NCCL, MPI, SHMEM; SerDes, packaging, optics and reach constraints.