Physical Design Engineer

About the role

eInfochips, an Arrow company, is hiring a Physical Design Engineer for a fully on-site position in San Jose, California. The engineer works on ASIC chip partitions, collaborating with architects, RTL designers and DFT engineers to deliver implementation and signoff within strict schedules.

Key responsibilities

• Execute synthesis, PNR and STA for assigned ASIC chip partitions according to schedule and design goals.
• Resolve implementation and signoff issues with architects, RTL designers and DFT engineers.
• Help close EM/IR, drive LEC and support physical verification signoff in coordination with methodology owners.
• Proactively identify physical design challenges with the design team and contribute to refining implementation and physical design methodologies, including synthesis, PnR, EMIR, PDN and LEC.
• Troubleshoot flow issues and work with EDA vendors to resolve them.

Required profile

• Bachelor's degree in electrical engineering, computer engineering, computer science or a related field, or equivalent practical experience.
• 7+ years of hands-on experience in physical design and implementation, including synthesis, PnR, timing convergence and physical verification.
• Experience in SoC design and implementation.
• Ability to adhere to tight schedules and apply low-power design techniques.
• Expertise in sub-7nm node technologies.

Required skills

• Proficiency with EDA tools such as Innovus, Tempus and Quantus.
• Strong TCL scripting to build custom flows on Cadence/Synopsys tools.

What we offer

• Competitive compensation and a benefits package including medical, dental and vision insurance.
• 401k with matching contributions, short- and long-term disability insurance.
• HSA/HRA options and paid time off.
• Tuition reimbursement and growth opportunities.