Design For Test Engineer IV (IC)

About the role

eInfochips, an Arrow company, is looking for a Design For Test Engineer IV (IC) in San Jose, California. The role covers DFT implementation for 3nm and 5nm networking chips, including scan insertion, ATPG pattern generation, MBIST and JTAG insertion, and debugging. The position is full-time and fully on-site, with the ability to travel to a client office as requested.

Key responsibilities

• DFT implementation for 3nm and 5nm networking chips and IP DFT work
• RTL checks for scan-insertion compatibility using Synopsys Spyglass
• Scan insertion using Tessent TestKompress
• ATPG pattern generation in compressed and uncompressed mode
• Pattern simulation with and without timing for different corners
• Mismatch debug using Verdi
• Scripting with Perl, Shell and TCL to enhance the DFT flow and Makefiles
• MBIST insertion and verification on blocks and top silicon, and IEEE 1149.1 JTAG insertion and verification

Required profile

• 5 to 7 years of experience in DFT
• Experience with multi-million gate count SoCs in networking, consumer and IP areas such as PLL and SerDes
• B. Tech or M.Tech in Microelectronics/Electronics
• Excellent communicator

Required skills

• Scan insertion, ATPG, GLS and pattern simulation (with and without timing)
• MBIST insertion and verification
• IEEE 1149.1 JTAG insertion and verification
• Scripting in Perl, Shell and TCL
• Tools: Mentor Tessent, Cadence Modus, Synopsys Tetramax, Synopsys Spyglass, VCS, Verdi

What we offer

• Hiring range of $112,200 to $170,500, depending on location, experience, education and skills
• Medical, dental and vision insurance, 401k with matching contributions, and disability insurance
• HSA/HRA options, paid time off and tuition reimbursement