Physical Design Engineer

About the role

Cerebras Systems builds a large AI chip and is hiring a Physical Design Engineer in Sunnyvale. The engineer drives high-impact power, performance and area (PPA) strategy together with the RTL team, owns all disciplines of physical design and implementation from RTL to tapeout, and ensures blocks integrate into the full-chip architecture.

Required profile

• 7+ years of physical design and physical verification experience.
• BS or MS in Electrical Engineering.
• Strong background in STA, constraint drafting and timing convergence at block, partition and full-chip levels.
• Good understanding of full-chip floor planning and integration.
• Ability to work with RTL teams to optimize for physical design.

Required skills

• Expertise with ICV or Calibre tools for DRC and LVS, and with IR/EM analysis and resolution.
• Strong knowledge of block-level and full-chip physical verification methodology.
• Experience with the complete physical design flow and block/subsystem timing closure.
• Scripting in Tcl and Python, with ability to enhance flows.
• Design Compiler, Fusion Compiler, ICC2 or similar tools.
• Preferred: high-speed CPU/GPU design, high-speed IO and third-party IP integration, block/partition PD and PDV, Synopsys tool suite.

The salary range is $180,000 - $280,000 per year, depending on experience, skills and location.