Lead RTL Design Engineer

About the role

Cerebras Systems builds the world's largest AI chip, the Wafer Scale Engine (WSE), which delivers training and inference speeds over 10 times faster than GPU-based cloud services. As a lead front-end design engineer, you will join a world-class team designing the next generation of WSE chips. The role requires deep expertise in RTL design and integration, with close collaboration and management of an external ASIC vendor, and work with design verification, physical design, software and system teams.

Key responsibilities

• Drive all aspects of chip design, including functional specification, micro-architecture, RTL development and synthesis.
• Manage the external ASIC vendor through the product development cycle.
• Work with the physical design team to achieve design closure and meet PPA goals.
• Work with design verification and DFT teams to achieve the best functional and test coverage.
• Work with software and system teams to deliver optimal performance and feature set.
• Debug silicon-level functional, timing and power issues during bring-up.

Required profile

• Master's degree in Computer Science, Electrical Engineering or equivalent.
• 8-15 years of experience delivering complex, high-performance RTL designs.
• Proven track record of multiple silicon successes.
• Experience collaborating and managing external vendors.
• Experience with FPGA development toolchain (Place and Route, floor planning, timing analysis) is a plus.
• Hybrid work environment.

Required skills

• Front-end chip integration and third-party IP integration.
• Networking, high-performance computing, machine learning or related fields.
• High-speed IO and networking stacks including TCP/IP, RDMA and Ethernet.
• Knowledge of PCIe, CPU interfaces and SerDes.
• Working knowledge of Python and TCL.

The base salary range is $200,000 to $299,000 per year, with possible bonus and equity depending on experience, skills and qualifications.