Senior Logic Design Engineer (RTL, FPGA/ASIC)

About the role

An international technology company developing advanced control and measurement systems for quantum computing is looking for an experienced Expert/Senior Logic Design Engineer. The role contributes to next-generation FPGA and ASIC-based control platforms, designing and optimizing high-performance digital logic with strict latency and timing requirements. It is a remote position open to candidates in Ukraine, Romania, Bulgaria, Poland and the Czech Republic.

Key responsibilities

• Design and implement configurable, low-latency RTL modules using SystemVerilog.
• Develop digital logic for FPGA and ASIC applications, including signal processing, waveform generation and real-time control.
• Take part in the full RTL lifecycle, from architecture and microarchitecture definition through implementation and verification.
• Optimize RTL designs for timing, latency, resource utilization and power efficiency.
• Perform logic synthesis, timing analysis and optimization to meet design constraints.
• Work with verification engineers to ensure functional correctness and test coverage.
• Analyze system and software requirements and implement hardware-software interfaces.
• Integrate proprietary digital IP into FPGA/ASIC architectures and take part in design reviews and process improvements.

Required profile

• Bachelor's or Master's degree in Electrical or Computer Engineering, or equivalent practical experience.
• 4+ years of professional experience in FPGA or ASIC digital logic design.
• Strong practical experience in RTL development with SystemVerilog (mandatory).
• English sufficient for collaboration in an international engineering team.

Required skills

• Logic synthesis, static timing analysis (STA) and timing optimization.
• Clock-domain crossing (CDC), synchronous digital design and hardware interfaces.
• Simulation-based RTL verification and debugging.
• Nice to have: AMD/Xilinx FPGA (especially Versal) and Vivado; Synopsys VCS or Siemens Questa; DSP, waveform generation or high-speed data acquisition; AXI, PCIe, DDR interfaces; ASIC RTL and reusable IP; Python, Tcl or similar automation scripts; hardware-software co-design; quantum computing, telecoms or measurement equipment experience.