Senior Design Verification Engineer (SV/UVM)

About the role

eInfochips, a company of Arrow, is looking for a senior Design Verification Engineer in San Jose, CA. The role is fully onsite and involves executing complete verification projects with hands-on experience, mentoring, client interaction, technical reviews and close tracking of both technical and management aspects.

Key responsibilities

• Guide the team in developing UVM-based SystemVerilog test benches
• Define block, subsystem and SOC-level test plans, including PCIe, NVMe, NAND, DDR and CPU subsystems
• Define verification methodologies, flows and quality metrics
• Mentor colleagues and provide informal guidance to junior staff
• Represent the senior level where a career can stabilize for many years

Required profile

• Typically 5-7 years of related experience with a 4-year degree, or 3 years with an advanced degree, or equivalent experience
• Ability to work independently with minimal guidance and to solve complex problems
• Experience mentoring others and contributing to process improvements

Required skills

• Strong SystemVerilog and UVM expertise
• AXI, NOC, Ethernet, PCIe, UCIe switch expertise
• CPU ARM/RISC-V with C knowledge
• Regression and coverage closure

What we offer

• Hiring range of $95,900 to $149,600, depending on location, experience, education and skill level
• Medical, dental and vision insurance
• 401k with matching contributions
• Short-term and long-term disability insurance
• HSA/HRA options and paid time off
• Tuition reimbursement and growth opportunities