Principal Circuit Designer - Analog / SERDES (Automotive Transceivers)

About the role

NXP is looking for a Principal or Senior Principal Circuit Designer to design and deliver high-speed, high-linearity analog and SERDES circuit blocks that form the Analog Front End (AFE) of automotive transceivers. This is a hands-on individual contributor role in San Jose, CA, with a hybrid arrangement of 3 days in the office and 2 days working from home; it is not open to 100% remote work. The Senior Principal scope also includes technical leadership, influencing architecture and mentoring other designers.

Key responsibilities

• Architect, design and simulate analog circuit blocks for the AFE: transmit circuits (line drivers, pre-drivers, output stages), receive circuits (front-end amplifiers, CTLE, PGA, slicers) and clocking circuits (PLLs, DLLs, clock distribution, jitter filtering).
• Translate system and PHY requirements into block-level specifications and optimize designs for linearity, noise, jitter, power, area and robustness.
• Run detailed transistor-level simulations across PVT corners and the full automotive temperature range.
• Support silicon bring-up, characterization and validation, correlate simulation results with silicon measurements and drive design improvements.
• Work with layout, digital, DSP, systems, test and product engineering teams and resolve performance, yield and reliability issues through root-cause analysis.
• Lead technical design reviews, influence AFE and PHY architecture decisions and mentor senior and mid-level designers.

Required profile

• MSEE or PhD in Electrical Engineering or equivalent (strongly preferred).
• 12-15+ years of experience in analog or mixed-signal IC design (Principal); 15-20+ years for Senior Principal.
• Proven hands-on experience designing high-speed SERDES or wireline analog circuits and delivering TX, RX and clocking circuits to production silicon.
• Extensive experience with circuit design, simulation and debug at the transistor level.

Required skills

• High-speed TX and RX circuit design, linearity, distortion and noise analysis.
• Jitter generation, tolerance and clock integrity; PLL/DLL and clocking architectures.
• PVT variation and automotive robustness; advanced CMOS processes for high-speed analog.
• Highly desired: 10GBASE-T, 10GBASE-T1 (automotive Ethernet), TDD-based transceivers, AEC-Q100, automotive production ramp and customer qualification, and ISO 26262 exposure.

What we offer

• Base salary range of $191,500 to $263,300 per year (California only).
• Health, dental and vision insurance, 401(k) and paid leave.
• Competitive benefits, incentive compensation and/or equity for certain roles.