Principal AI Accelerator Architect Lead

About the role

Analog Devices is looking for a technology expert in analog and digital AI accelerators to define and develop an innovative approach to AI compute that is ultra-low power and deeply integrated in silicon. This hands-on technical leadership role focuses on how intelligence is represented, computed and executed on a chip under strict power, latency and reliability constraints. It sits in the MicroAI team and is open to Boston, MA and San Jose, CA.

Key responsibilities

• Translate product requirements, functions and workloads into end-to-end system architectures, with specifications for IP blocks, processors, firmware, memory subsystems and AI compute engines.
• Explore new representations of intelligence beyond conventional digital AI models and architectures.
• Bridge the gap between academic research and real-world deployment, accounting for noise, power, variability, node scalability and manufacturability.
• Lead architecture exploration and collaborate with the modeling team to drive insights and breakthroughs.
• Define detailed hardware block specifications and interfaces, contributing to modeling and, when appropriate, RTL development.
• Work with architecture, design, verification, firmware and physical design teams so architectural intent is realized.
• Provide technical leadership and mentorship across multiple projects and SoC generations.

Required profile

• PhD or Master's degree in Computer Engineering, Electrical Engineering or a related technical field.
• 10+ years of practical experience in digital and analog AI accelerator systems architecture for physical AI or embedded intelligent platforms (robotics/drones, AV systems).
• Leadership and management experience.
• Proven ASIC design expertise, including high-speed and low-power RTL development, SystemVerilog for analog compute, and physical design flows and constraints.
• Strong expertise in SystemC modeling and virtual prototyping, with complex system-level models built and analyzed.
• Deep understanding of processor architecture: datapaths, memory hierarchies, interconnects, peripherals and chip-level interfaces.
• Advanced verification methods: UVM, SystemVerilog, constrained-random testing, functional coverage and assertion-based verification.
• Programming in C and other modeling/simulation languages, and excellent communication skills.

What we offer

• Expected new-hire wage range of $200,000 to $275,000, with possible variation by location, experience and market conditions.
• Discretionary performance-based bonus.
• Medical, vision and dental coverage, 401k, paid vacation, holidays and sick time.
• 10% travel requirement, first shift, days.