SOC Architect – AR/AI Wearable Chip Design

About the role

Reality Labs Silicon is seeking a senior SOC Architect to lead the definition of next‑generation system‑on‑chip architectures for AR and AI wearable devices. You will shape the overall chip architecture, balancing performance, power, and size constraints to enable immersive mixed‑reality experiences.

Key responsibilities

• Define and drive SOC‑level architecture for wearable chips, covering compute subsystems, memory hierarchy, interconnect topology, and power delivery.
• Lead architectural exploration and trade‑off analysis across heterogeneous blocks such as CPU, GPU, vision, audio, and ML accelerators.
• Collaborate with algorithms, firmware, and software teams to enable hardware‑software co‑design for latency‑critical workloads.
• Partner with IP vendors and internal design teams to evaluate and integrate third‑party and custom IP blocks.
• Develop architectural specifications, interface definitions, and design guidelines for RTL and physical design teams.
• Provide technical direction to engineers across silicon, systems, and platform groups.
• Contribute to long‑term silicon roadmap by assessing emerging process, memory, and compute technologies for AR/VR.

Required profile

• Bachelor’s degree in Computer Science, Computer Engineering, or related field, or equivalent experience.
• 8+ years of experience in SOC architecture, micro‑architecture definition, or system‑level hardware design for consumer electronics or mobile/wearable platforms.
• Proven experience architecting heterogeneous SOCs that include CPU, GPU, neural processing, and custom accelerators.

Required skills

• High‑speed I/O interfaces: PCIe, USB, LPDDR.
• Memory subsystem architecture: cache hierarchy design, DRAM interface optimization, on‑chip interconnect (NoC) design.
• Expertise in CPU, GPU, and AI/ML accelerator architecture.
• Experience with power‑aware design and thermal budgeting for wearable devices.