Digital Verification Engineer

About the role

At Nexthop AI, ensuring the correctness of digital logic is critical. The Digital Verification Engineer will own verification environments and test suites that prove our FPGA and ASIC subsystems behave exactly as designed, working closely with RTL designers and firmware engineers.

Key responsibilities

• Design, build, and maintain reusable verification environments for block‑level to full‑chip integration.
• Create behavioral/reference models to predict expected DUT behavior.
• Develop directed and constrained‑random test suites, define coverage goals, and drive coverage closure.
• Embed SystemVerilog Assertions (SVA) to catch protocol violations.
• Run and debug simulations using Modelsim/Questasim and NC‑Verilog, triage failures, and collaborate on fixes.
• Set up and maintain fast, deterministic regression suites.
• Support FPGA and board bring‑up, correlating simulation results with hardware.
• Partner with firmware/software teams during system bring‑up and validate register maps and interfaces.
• Document verification exit criteria and contribute to design milestone sign‑offs.

Required profile

• 3–7 years of digital verification experience on FPGA or ASIC designs.
• Strong proficiency in Verilog and SystemVerilog.
• Experience with simulation tools such as Modelsim, Questasim, and NC‑Verilog.
• Hands‑on knowledge of constrained‑random test development and functional/code coverage.
• Ability to work closely with RTL designers and firmware engineers to resolve issues.

Required skills

• Verilog
• SystemVerilog
• SystemVerilog Assertions (SVA)
• Modelsim / Questasim
• NC‑Verilog
• FPGA verification
• ASIC verification