RFIC Silicon Lead

About the role

We are looking for our first silicon hire to define the RF CMOS architecture for an ultra‑low‑power, frequency‑agile sensing front‑end. The role will start hands‑on at the transistor level, building the design environment, evaluating processes, and creating critical RF blocks that meet Tacit’s sensing and machine‑learning constraints.

Key responsibilities

• Define the overall RF CMOS architecture for a low‑power, wide‑band SoC.
• Translate system‑level sensing, ML and form‑factor requirements into circuit specifications.
• Design or technically lead the implementation of VCOs, PLLs, mixers, LNAs, buffers, passives, clocking, biasing and power‑management blocks.
• Develop fast‑settling frequency‑generation and hopping schemes for aggressive duty‑cycled operation.
• Drive power‑reduction techniques across the RF chain, including supply gating, bias trimming and wake/sleep transients.
• Evaluate and recommend CMOS process options (28 nm, 22FDX, 55 nm RF) and set up the Cadence Virtuoso design flow.
• Identify architectures that will not close in silicon and propose practical alternatives.
• Own or technically direct tape‑out, packaging, bring‑up, measurement correlation and iteration.

Required profile

• Deep expertise in low‑power CMOS RF circuit design and system architecture.
• Ability to reason across sensing, machine‑learning constraints and silicon feasibility.
• Experience leading or building a silicon team, and collaborating with external silicon partners.
• Strong problem‑solving skills and architectural judgment for ultra‑low‑power applications.

Required skills

• CMOS RF design
• RF front‑end architecture
• Voltage‑controlled oscillators (VCO)
• Phase‑locked loops (PLL)
• Mixers and low‑noise amplifiers (LNA)
• Cadence Virtuoso and Spectre simulation
• Calibre DRC/LVS and EM simulation tools
• PDK flow management
• Low‑power design methodologies
• Process evaluation for 28 nm, 22FDX, 55 nm RF nodes