Senior DSP System Engineer (MEO Satellite Payloads)

About the role

meoSphere is SES's next-generation Medium Earth Orbit satellite constellation delivering secure connectivity to governments, enterprises and commercial customers, and high-speed broadband to close global connectivity gaps. As a DSP System Engineer you will design, analyse, model and validate signal processing blocks implemented in ASIC and FPGA technology in satellite payloads, working in an agile software/firmware and hardware team. The first six months focus on modelling algorithms for digital beamforming ASICs and 5G NTN waveform processing, and within two years the algorithms and models will fly in space.

Key responsibilities

• Develop and model DSP algorithms for digital beamforming, channelization, MIMO, DPD, CFR, calibration and digital compensation in phased-array and satellite systems.
• Develop DUC/DDC blocks with multi-rate DSP techniques, optimised for low-power fixed-point hardware (FPGA/ASIC).
• Create system-level MATLAB/Python/C++ models of end-to-end RF and baseband processing, and turn requirements into implementable DSP blocks for ASIC design, working with RTL and physical design teams.
• Evaluate fixed-point versus floating-point trade-offs and develop hardware/software co-design models partitioning algorithms between firmware, digital logic and analog front end.
• Prototype and validate performance on FPGA or simulation platforms, and support pre-silicon and post-silicon validation.
• Optimise algorithms for low power and high throughput, and support beamforming calibration strategies.
• Produce technical reports, design documentation and test plans.

Required profile

• MS/PhD in Electrical Engineering, Signal Processing or a related field with 5 years of DSP algorithm design experience.
• Proven background in digital beamforming, MIMO and calibration algorithms for phased arrays.
• Experience in lab-based silicon bring-up, calibration and verification of beamforming performance.
• Eligibility for ESA/EU/NATO/National SECRET security clearance, which is an asset.
• Able to travel nationally and internationally.

Required skills

• System-level modelling in MATLAB/Simulink and Python, including model-based design.
• DSP simulation in C/C++ or SystemC, especially fixed-point modelling.
• Familiarity with ASIC flow integration (RTL handoff, verification, bit-accurate modelling) and FPGA prototyping.
• Nice to have: digital communications theory, antenna array processing, and understanding of radiation and thermal constraints for satellite ASICs.

Salary range for the full-time position: $150,000 - $190,000 plus bonus and benefits, depending on location and experience.