Senior Digital Design Engineer

About the role

Analog Devices is hiring a Senior Digital Design Engineer in Nova. The role owns the end-to-end physical implementation of major IP blocks and/or full-chip designs, aligned with the company's Career Development Framework, and involves mentoring junior engineers.

Key responsibilities

• Develop and optimize floorplans (macro placement, IO ring planning, power grid design, congestion/area/timing analysis).
• Execute place-and-route, clock tree synthesis and timing closure using Cadence Innovus.
• Run detailed static timing analysis (STA) and drive sign-off across PVT corners and operating modes.
• Resolve physical verification issues (DRC/LVS/ERC) with process, CAD and foundry teams.
• Automate design flows (hierarchical PNR, IO ring automation, Flash PG) and contribute to continuous flow improvements.
• Work with RTL, DFT, verification, package and library teams to meet PPA targets and milestones.
• Mentor and coach junior engineers, document methodologies and share best practices.

Required profile

• Bachelor's or Master's degree in Electrical/Electronics Engineering or a related discipline.
• 5+ years of hands-on ASIC/SoC physical design at advanced nodes (40, 28, 22, 16 nm and similar).
• Strong knowledge of fabrication process limitations, ESD/IR/EM analysis and sign-off methodologies.
• Ability to communicate clearly, collaborate cross-functionally and adapt to fast-paced, changing needs.
• Preferred: hierarchical design and large-scale SoC integration, EDA synthesis and formal equivalence checking, and low-power/multi-voltage methods (UPF/CPF).

Required skills

• Floorplanning, PNR and STA with industry EDA tools (Cadence Innovus)
• Physical verification (DRC/LVS/ERC)
• Automated flows in Tcl, Perl or Python

Travel is required about 10% of the time, on the first shift. Export licensing review may apply for non-US citizens or permanent residents.