Principal Synthesis & STA Engineer (P5)

About the role

Analog Devices is looking for a P5 Synthesis & STA Engineer to lead Synthesis, Static Timing Analysis (STA) and timing closure for complex, high-performance SoCs with large digital and analog interfaces. The role drives full-chip timing analysis and closure, establishes robust top-down closure methodologies and solves complex QoR challenges across RTL, synthesis, constraints, clocking and physical implementation. It also involves mentoring engineers into leadership roles.

Key responsibilities

• Lead and own Synthesis and STA closure for complex, multi-GHz SoCs at IP, subsystem, partition and full-chip levels.
• Develop, validate and review complex timing constraints across the hierarchy, and drive full-chip timing signoff across multi-mode, multi-corner scenarios.
• Establish a top-down timing closure methodology covering constraints, budgets, interface timing and convergence.
• Apply AOCV/SOCV methodologies, variation-aware timing analysis and advanced-node timing signoff.
• Drive top-level clock planning and balancing, working with Physical Design teams on clock topology, implementation and routing.
• Root-cause recurring timing and QoR issues across RTL, synthesis, constraints, DFT, clocking, placement, CTS, routing, extraction and signoff, and drive timing ECO strategies using automated and manual techniques.
• Understand Scan/DFT architectures and their timing implications, and build scalable automation and analysis methodologies.

Required profile

• Bachelor's or Master's degree in Electrical or Computer Engineering.
• 10-15 years of relevant experience.
• Proven experience owning IP, subsystem, partition and full-chip timing convergence and signoff.
• Experience leading multiple successful advanced-node tapeouts.

Required skills

• Deep hands-on expertise in Digital Synthesis, STA and timing closure for advanced-process SoCs, preferably 16nm and below.
• AOCV/SOCV methodologies and hierarchical timing constraint development and debugging.
• Clock-tree analysis, clock latency/skew, clock uncertainty and clock balancing.
• RTL-to-GDS flow: floorplanning, placement, CTS, routing, extraction, physical verification, EM/IR and signoff.
• Leakage and dynamic power optimization, and automated and manual timing ECO techniques.

The role requires travel about 10% of the time and works on the first shift. Positions requiring access to technical data may require export licensing review.