Principal Digital DFT Engineer

About the role

Analog Devices is looking for a Principal Digital DFT Engineer to architect, implement and verify advanced DFT solutions for complex digital ASICs and SoCs. The role focuses on direct technical execution, deep problem solving and ownership of DFT flows to ensure robust testability and manufacturing yield. It is a day-shift position with about 10% travel.

Key responsibilities

• Own and drive DFT architecture, definition and implementation for digital chips, including scan insertion, ATPG, boundary scan, MBIST, logic BIST, JTAG and test compression.
• Run EDA tools for scan synthesis, test pattern generation, fault simulation and DFT rule checks.
• Create and validate test plans covering stuck-at, transition and critical-path faults.
• Integrate DFT with RTL and physical design teams and resolve trade-offs affecting fault coverage, PPA and manufacturability.
• Optimize test modes, design for manufacturability and debug silicon failures from bring-up through production ramp.
• Develop low-overhead test structures and warranty schemes for new and legacy IP.
• Debug DFT issues in simulation, emulation and the lab, and deliver documented architectures, test strategies, TCL/Python/Perl scripts and design guidelines.
• Work with ATE test engineers to cut test costs and improve coverage, and mentor engineers in DFT methodology.

Required profile

• Bachelor's or Master's degree in Electrical/Electronics/VLSI Engineering or equivalent.
• 10+ years of hands-on DFT experience for digital ASIC/SoC, with multiple tapeouts of large designs.
• Expert DFT flows (scan, ATPG, MBIST, BIST, JTAG, boundary scan, fault simulation).
• Solid knowledge of RTL design, synthesis, timing and SoC architecture constraints.
• Ability to debug complex DFT and test-mode issues at lab and production level, and to document and mentor junior engineers.

Required skills

• EDA tools: Synopsys DFT Compiler, Tessent, Cadence Modus or equivalent.
• Scripting in TCL, Python and Perl for DFT automation and reporting.
• Nice to have: advanced-node DFT (<=7nm), 2.5D/3D packaging, ISO 26262, memory BIST and ATE pattern development.