Patterning Process Engineer

About the role

As a Process Engineer, you'll play a crucial role in designing and optimizing manufacturing processes for display and semiconductor technologies. You will collect and analyze data, perform hardware characterization, troubleshoot issues, and collaborate with internal and external partners to advance patterning technology.

Key responsibilities

• Develop and optimize new or modified patterning test vehicle flows for advanced patterning technology.
• Compile, analyze, and evaluate experimental data to establish process windows, specifications, and material requirements.
• Provide technical leadership for continuous improvement of advanced patterning short‑loop processes.
• Drive improvements in critical dimension (CD), CD uniformity (CDU), line edge roughness (LER), line width roughness (LWR), depth of focus (DOF), exposure latitude, SPC, yield, and defectivity.
• Partner with process and integration engineering teams to develop integrated flows, troubleshoot challenges, perform root‑cause analysis, and resolve complex issues.
• Collaborate with external partners on joint development programs, designing experiments, analyzing data, and preparing technical reports.
• Engage with internal and external customers to address complex engineering challenges and communicate technical findings.

Required profile

• Bachelor's degree in Chemistry, Physics, Materials Science, Chemical Engineering, or related field.
• 4 to 7 years of semiconductor experience in advanced lithography, patterning, or process development.
• Proven ability to solve complex technical problems through strong analytical skills and hands‑on experimentation.
• Excellent communication and collaboration skills across cross‑functional teams.

Required skills

• Advanced lithography and patterning techniques
• Semiconductor process development
• Data analysis and statistical process control (SPC)
• Hardware characterization
• Critical dimension (CD) measurement
• CD uniformity (CDU) assessment
• Line edge roughness (LER) evaluation
• Line width roughness (LWR) evaluation
• Depth of focus (DOF) analysis
• Exposure latitude optimization
• Yield analysis
• Defectivity analysis

What we offer

• Competitive salary range of $124,000 – $171,000 per year.
• Location in Santa Clara, CA with a supportive onsite work culture.
• Comprehensive health, wellbeing, and professional development programs.