Design Verification Engineer (eInfochips)

About the role

eInfochips, a company of Arrow, is hiring a Design Verification Engineer in San Jose, California. The role covers the complete verification cycle of digital designs, from test plan development through coverage closure, and requires at least 6 years of experience. The position is fully on-site.

Key responsibilities

• Develop test plans and build BFM, driver, monitor and scoreboard components integrated into the test bench
• Run stress and corner testing, perform failure debugging and gate-level simulations
• Write assertions and achieve verification closure with the team
• Report to the customer on daily or weekly progress and ensure customer satisfaction

Required profile

• At least 6 years of experience in System Verilog hardware verification languages and C++/C
• At least 6 years of experience in UVM
• Ability to work fully on site in San Jose, including travel to an Arrow client office when requested

Required skills

• System Verilog and C++/C
• UVM and SVTB/UVM testbenches
• Debug and assertion coding
• Make, Perl, Python or other scripting languages are a plus
• Protocol experience is fine; Subversion and Bugzilla are a plus
• Understanding of DSP is a plus

What we offer

• Competitive compensation and a benefits package
• Medical, dental and vision insurance
• 401k with matching contributions
• Short-term and long-term disability insurance
• HSA/HRA options and paid time off
• Tuition reimbursement and growth opportunities