Senior Module Engineer, Hybrid Bonding

About the role

Applied Materials is seeking a highly motivated Die-to-Wafer Hybrid Bonding Module Engineer to develop and scale next-generation hybrid bonding technologies for advanced semiconductor packaging, including memory, chiplets, AI accelerators, photonics and heterogeneous integration platforms. The role leads process module development across die preparation, surface activation, die placement, hybrid bonding, post-bond characterization, yield improvement and manufacturing scale-up, working closely with equipment development teams, process integration engineers, materials scientists, device architects and external partners.

Key responsibilities

• Develop and optimize die-to-wafer hybrid bonding processes, setting process windows for surface preparation, plasma activation, die placement, alignment and overlay control, bonding temperature and pressure, and post-bond annealing, driving Cu-Cu and dielectric-dielectric interconnect formation.
• Integrate hybrid bonding into memory architectures, chiplet systems, silicon interposers, SoW platforms and co-packaged optics, resolving process interactions and yield excursions.
• Reduce yield and defects by identifying root causes of bond voids, die shift, overlay errors, non-uniform bonding and particle contamination, using DOE and statistical process control.
• Characterize bonding quality with CSAM, X-ray inspection, FIB/SEM, optical metrology and electrical test structures, correlating process parameters with package performance.
• Work with equipment teams on hybrid bonding systems, die placement tools, plasma activation modules, surface preparation modules and integrated process control, and evaluate next-generation bonding platforms.
• Define and run reliability tests (thermal cycling, HTOL, mechanical pull/shear, moisture sensitivity) and drive failure analysis.
• Lead cross-functional projects from concept to technology transfer, publish technical results, present progress to engineering leadership and customers, and mentor junior engineers.

Required profile

• M.S. in Materials Science, Electrical, Mechanical, Chemical or Physics Engineering, or Semiconductor Manufacturing, or Ph.D. in one of these fields.
• Minimum 5+ years of semiconductor process development experience after the graduate degree.
• Direct experience in hybrid bonding, thermocompression bonding, wafer bonding, advanced packaging, HBM development, Cu interconnect technology or chiplet integration.
• Preferred: Ph.D. with 5+ years of industry experience, HBM or 3D stacking experience, DBI and die placement system experience, knowledge of AI/HPC packaging architectures, 200 mm and 300 mm wafer experience, and a track record of patents, publications or conference presentations.

Required skills

• Cu-Cu interconnect formation, surface chemistry and plasma activation, CMP and planarization, defect engineering, process integration and statistical process analysis.
• DOE and JMP/Minitab analysis tools.
• Familiarity with metrology and failure analysis techniques.

What we offer

• Salary of $147,000 to $202,500.
• Full-time position with relocation eligibility and travel of up to 10% of the time.
• Comprehensive benefits package, with possible bonus and stock award program participation.